(a) Field of the Invention
The present invention generally relates to a semiconductor memory device having a redundancy function and, more specifically, to a discriminating circuit provided in the semiconductor memory device for judging whether or not a redundancy function has been used to substitute for a failed memory block.
(b) Description of the Related Art
Recently, a semiconductor memory device is generally designed to include redundant memory cells for a redundancy function to replace failed memory cells by the redundant memory cells, thereby enhancing the product yield of the memory device with an increased storage capacity. Such a semiconductor memory device is often provided with a roll call circuit for discriminating whether or not the redundant memory cells have been used, for the purpose of failure analysis or product evaluation.
FIG. 1 shows an example of a conventional roll call circuit, proposed in Patent Publication NO. JP-A-7(1995)-65595. The disclosed roll call circuit comprises a data output block DO1, a first read circuit 13 for reading data from a sense amplifier block, and a second read circuit 16 for reading the result of a roll call test. The data output block DO1 amplifies data on a write/read bus line pair WRBT/WRBN and outputs the amplified data through I/O pads. The first read circuit 13 receives data from the sense amplifier block (not illustrated) and outputs the data through the bus line pair WRBT/WRBN. The second read circuit 16 outputs the result of the roll call test to the bus line pair WRBT/WRBN.
The proposed roll call circuit further comprises a redundancy decoder 17, an X-decoder 18 and a roll call decoder 14. The redundancy decoder 17 receives through external pins A1-An (not-illustrated) address signals ADD1-ADDn, which are "High" or "Low" depending on "1" or "0" given to the external pins A1-An. The X-decoder 18 receives an address signal ADD0 which is "High" or "Low" depending on the signal given to an external pin A0, the address signals ADD1-ADDn and a signal RDS output from the redundancy decoder 17. The roll call decoder 14 receives the signal RDS from the redundancy decoder 17, a signal YRD from an address transition detector ("ATD") 19 and a test mode signal TM for allowing the memory device enter into a test mode.
The first read circuit 13 comprises a pair of N-channel transistors T20 and T21 and a NOR gate N04. The pair of n-channel transistors T20 and T21 function as transfer gates between a data line pair RBT/RBN from the sense amplifier block and the bus line pair WRBT/WRBN. The NOR gate N04 receives a signal RCE from the second read circuit 16 and a signal BSLB at the inputs thereof, and supplies an output signal to the gate of the transistors T20 and T21.
The second read circuit 16 comprises a NOR gate NO3 and a pair of N-channel transistors T18 and T19. The NOR gate NO3 receives a signal RCSB from the roll call decoder 14 and a test mode signal TM at the inputs thereof. The transistor T18 receives the signal RCE at the gate electrode thereof from the NOR gate NO3 and functions as a transfer gate between the ground ("GND") and the bus line WRBN. The transistor T19 functions as the transfer gate between the source line and the bus line WRBT.
The bus line pair WRBT/WRBN are clamped to the power source level by a clamp circuit 15 comprising gate-grounded pair of P-channel transistors T7 and T8 having a relatively small capacity for supplying a small charging current.
In a normal read operation mode of the proposed roll call circuit, the test mode signal TM is "High" since it is "Low" only during a roll call test, and therefore, the signal RCE is "Low". It follows that the N-channel transistors T20 and T21 are "ON" for a period while the input signal BSLB is "Low", and data supplied from the sense amplifier block through the data line pair RBT/RBN are fed to the I/O pads through the bus line pair WRBT/WRBN and the data output block DO1. In this case, no data are delivered to the bus line pair WRBT/WRBN from the second read circuit 16, because the signal RCE is "Low" and accordingly the transistors T18 and T19 are "OFF".
In operation for a roll call test mode, since the test mode signal TM is "Low" during the roll call test, data on the bus line pair WRBT/WRBN are determined in accordance with the level of the signal RCSB. If the signal RCSB is "Low", then the signal RCE is "High", causing the transistors T18 and T19 to be "ON", and the transistors T20 and T21 to be "OFF", thereby maintaining WRBT at "High" and WRBN at "Low". These data on the bus line pair WRBT/WRBN are delivered to the I/O pads through the data output block DO1. On the contrary, if the signal RCSB is "High", then the transistors T18 and T19 are "OFF" and the transistors T20 and T21 are "ON" for a period while the signal BSLB is "Low". The data from the sense amplifier block are, therefore, delivered to the I/O pads through the bus line pair WRBT/WRBN and the data output block DO1.
The X-decoder 18 decides which digit line is to be selected, in accordance with the address signals ADD0 and ADD1-ADD9. The redundancy decoder 17 decides whether or not a redundancy digit line is to be selected. The address transition detector 19 generates a one-shot pre-charging signal YRD for a dynamic circuit in the roll call decoder 14. In the roll call test mode, the roll call decoder 14 generates the output signal RCSB depending on the result of the roll call test. Accordingly, if data have been written into memory cells beforehand so that the data line RBT from the sense amplifier block is made "Low" and the data line RBN "High", the signal delivered to the I/O pads can be altered depending on "High" or "Low" of the signal RCSB. It follows that if the roll call test as described above is conducted while the combination of "High" and "Low" of the address signals ADD1-ADD9 is altered, it is possible to decide which redundant digit line has been used by determining the signals appearing on the I/O pads.
Referring to FIG. 2, the roll call decoder 14 shown in FIG. 1 comprises inverters I6-I8, a P-channel transistor T9, and N- channel transistors T22 and T23. The inverter I6 receives the one-shot pre-charging signal YRD, and the P-channel transistor T9 receives the test mode signal TM. The P-channel transistor T10 is connected in series with the transistor T9 between the source line and a pre-charge node, and receives an output signal from the inverter I6 at the gate thereof. The N-channel transistor T22, interposed between the pre-charge node and the GND, receives the test mode signal TM at the gate thereof. The N-channel transistor T23, connected in parallel with the transistor T22, receives the signal RDS from the redundancy decoder 7 at the gate thereof. The cascaded inverters I7 and I8 receiving an input signal from the pre-charge node raises the amplitude of the pre-charge node to thereby generate the output signal RCSB.
In operation of the roll call decoder 14 during a roll call test, since the test mode signal TM is "Low", the pre-charge node is pre-charged to the power source level during a high level of a one-shot signal YRD. However, if the signal RDS is "High", the level of the pre-charge node is determined by the resistance divisional ratio of the transistors T9, T10 and T23. The output signal RCSB is obtained by the inverter I7 having a ratio that makes the output "High" for that level of the pre-charge node, in association with the inverter I8. Since the test mode signal TM is "High" for the periods other than the roll call test, the pre-charge node is fixed at the GND level.
The signal RDS from the redundancy decoder 17 is "High" if the redundancy memory cells have been used, and "Low" if not. Accordingly, it is possible to judge whether or not the redundancy function has been used, by detecting the output signal of the redundancy decoder 17.
However, in a conventional semiconductor memory device of a type in which failed memory cells are replaced by redundant memory cells on a block-by-block basis, there exists no signal showing uniquely which memory cell block has been replaced because of the failure thereof. In this case, analysis of the cause of the failure is difficult.